1. Field of the Invention
The present invention relates to a TD (Time to Digital) converter that uses calculation in a time domain instead of using neither operational amplifier nor switched capacitor regarded as unsuitable for process scale shrinkage.
2. Description of the Related Art
It is indispensable to develop an LSI that has lower power consumption, higher performance and lower cost than conventional ones for further development of information communication equipment. The performances of conventional LSIs have been improved in accordance with the scale shrinkage of semiconductor manufacturing processes. The mounted transistor count per chip increases every year by virtue of scale shrinkage, and this allows higher performance LSIs to be actualized.
However, the scale shrinkage becomes difficult due to dynamic range and the problem of nonlinearity in the analog circuits such as operational amplifiers and switched capacitors. In particular, under environments of low power voltages in the advanced processes, the dynamic range narrows and the linearity deteriorates, and this leads to difficulties in securing gain.
In recent years, a technology to shift calculations from the voltage domain to the time domain has been researched to perform AD (Analog to Digital) conversion without using analog elements such as operational amplifiers and capacitors for adaptation to scale shrinkage. As a technology to digitize time domain data, a Time-to-Digital Converter (TDC=TD converter) to digitally convert a delay value into a digital value has been known to those skilled in the art.
In view of the fact that a Gated-Ring-Oscillator TDC (hereinafter, referred to as a “GRO TDC”) utilizing a ring oscillator can obtain only first-order noise-shaping (See the Non-Patent Document 1), the present inventors have proposed operational-amplifier-less capacitor-less AD converter and TD converter capable of propagating quantization error in the time domain when taking advantage of the first-order noise-shaping characteristic of Δ-Σ modulation and performing higher-order noise-shaping (See the Patent Document 1 and the Non-Patent Document 2).
This is described hereinbelow. FIG. 19 shows a circuit configuration diagram of a GRO TDC. In the GRO TDC circuit, a pulse (Tin) is inputted as analog data changing temporally to a GRO (Gated-Ring-Oscillator), the inputted analog pulse width is quantized by counting the oscillation waveform of the GRO during the pulse width, and discretized digital data can be obtained. The present inventors paid attention to the first-order Δ-Σ type noise-shaping characteristic owned by the GRO TDC, and proposed an operational-amplifier-less capacitor-less AD converter capable of performing second-order noise-shaping (See FIG. 20). The proposed AD converter actualizes a second-order Δ-Σ modulator by employing a GRO TDC as a Δ-Σ modulator, a counter as a quantizer, and a D flip-flop as a circuit to propagate quantization error. The AD converter shown in FIG. 20 is configured to include a VT converter circuit part 14, a two-stage GRO 11 for inputting time domain data, a D flip-flop 12 that is inserted between the GRO 11 of the preceding stage and the GRO 11 of the succeeding stage and operates as a propagation circuit of delay information including the quantization error of the GRO 11 of the preceding stage, a counter 13 that counts the number of waves of the output oscillation waveforms (GROout1 and GROout2) from the GRO 11, a DSP (Digital Signal Processor) 15 that operates as an output signal generator part to generate an output signal based on the output count values (Dout1 and Dout2) from the counter 13, a reset part 17 configured to reset the D flip-flop 12 and two counter circuit parts 13 in response to a sampling clock (CK), and a calibration circuit 16 that performs nonlinear correction after a decimation filter process by the DSP 15.
In the above circuit configuration, the quantization error is included in the output oscillation waveform of the GRO 11, and the rise of an output oscillation waveform (GROout1) from the GRO of the preceding stage is detected by the D flip-flop 12 to obtain data (TQN1) that includes the quantization error (QN). Subsequently, by performing subtraction of only the value (Dout1) of counting oscillation in the DSP 15, the quantization error can be transmitted.
In the above circuit configuration, the gating operation (turning on and off of Tin and TQN1) of the GRO 11 adversely affects the internal phase information as switching noises. Moreover, the phase information is influenced by leakage currents of the transistors. Since the leakage currents tend to increase as the process scale shrinkage advances, the above circuit configuration is unsuitable for scale shrinkage.
The present inventors discovered such a problem that the phase information when the GRO 11 stops is not completely retained since the data of the retained quantization error deteriorates due to the influence of the leakage currents through the minute processes in the GRO 11 according to the results of analysis of the circuit operation of the GRO TDC.
Moreover, the present inventors discovered such a problem that the quantization error becomes nonlinear in the circuit in which the D flip-flop 12 is singly employed as the circuit to propagate the quantization error according to the results of analysis of the circuit operation of the GRO TDC.
Further, it was discovered that the noise-shaping effect is weakened by frequency mismatch between the GROs 11 of respective stages.
These problems become obstructions in increasing the resolutions of the TD converter and the AD converter.
Prior art documents which are related to the present invention are as follows:    Patent Document 1: Japanese patent laid-open publication No. JP 2011-108910 A;    Non-Patent Document 1: “A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping”, M. Z. Straayer, et al, IEEE Journal of Solid-state Circuits, Vol. 44, No. 4, pp. 1089-1098, April 2009; and    Non-Patent Document 2: “A 40-nm 640-μm2 45-dB Opampless all-digital second-order MASH ΔΣ ADC”, T. Konishi, H. Lee, S. Izumi, M. Yoshimoto, and H. Kawaguchi, IEEE ISCAS, pp. 518-521, May 2011.
As described above, the GRO TDC proposed by the present inventors, i.e., the operational-amplifier-less capacitor-less TD converter capable of performing higher-order noise-shaping by propagating the quantization error has such a problem that it easily receives influences on the gating operation of the GRO, the phase information when the GRO stops cannot be completely retained due to the influences of leakage currents, and the circuit to propagate the quantization error is nonlinear.